Neuromorphic crossbar · preprint
A Per-Chip Metadata Correction Framework for Neuromorphic Memristor Crossbars: Theoretical Architecture and Viability Analysis
Independent work, no institutional lab behind it — presented on its own terms.
Core idea
Device-to-device spread in memristor crossbars is treated as fabrication noise — minimized through tighter process control, hardware-aware retraining that couples models to hardware statistics, or statistical redundancy that accepts error as unavoidable.
Variability is a fixed, per-chip system property. Hadamard-structured excitation recovers the full deviation matrix in one factory pass; each node's gain α and offset δ are stored as compact metadata and applied to pre-compensate weights at model load — exact correction under linear response, with no retraining.
Pre-compensation computed once at model load. The device's physical offset cancels the programmed correction exactly — inference runs on the intended weight matrix with zero runtime cost.
Method
Apply N Hadamard input patterns through existing peripheral circuitry. Recover the full N × N conductance deviation matrix via a single matrix multiply — effective noise σeff = σmeas/√N.
Extract per-node α and δ from the identified deviation field. Store under Architecture A, B, or C — from 2 KB DCT coefficients to full per-node registers.
Any pre-trained model loads onto any characterised chip. Weights corrected once; heartbeat recalibration handles lifetime drift. No hardware-aware training required.
Storage architectures
Correction parameters α and δ alone — compressed from a 704 MB full characterisation record down to practical embedded sizes, exploiting spatial correlation from spin-coating physics.
Top K×K = 16×16 low-frequency DCT coefficients per matrix. Same basis as JPEG — spatially correlated variability concentrates in low frequencies.
99.8%+ variance captured · 31,250× compression
DCT smooth trend (2 KB) + column-level residual offsets (32 KB) + sparse outlier nodes stored explicitly (~29 KB for ≈0.03% of array).
99.97% variance captured · 319 ms dehash on ARM A53
Direct 8-bit α and δ per crosspoint with lossless spatial compression. Dehashing is a memory read — no reconstruction compute at load time.
3.12 ms dehash · lowest load-time cost
About
I'm an independent researcher based in Bangalore, working without an institutional lab affiliation. This paper is my own work — it is not affiliated with and sits outside my coursework at Kammavari Sangam Polytechnic (KSP), where I'm currently pursuing a diploma in Computer Science & Engineering. KSP has no involvement in this research.
The analyses are theoretical, grounded in published device parameters; experimental validation requires chip-level access identified as future work. On the experimental side, I'm in active dialogue with researchers at IISc's Centre for Nano Science and Engineering (CeNSE). Correspondence goes through my family company's email — I don't have an academic address yet.